full_adder

Modified

2025-11-11

Source: Lab2/full_adder.v (modified 2025-10-22 08:24)

// full_adder.v  (Verilog-2001)
module full_adder(
    input  A,
    input  B,
    input  Cin,
    output Sum,
    output Cout
);
    // Sum = A'B'Cin + A'BCin' + AB'Cin' + ABCin
    assign Sum  = (~A & ~B &  Cin) |
                  (~A &  B & ~Cin) |
                  ( A & ~B & ~Cin) |
                  ( A &  B &  Cin);

    // Cout = AB + ACin + BCin
    assign Cout = (A & B) | (A & Cin) | (B & Cin);
endmodule